1. Field of the Invention
The present invention relates to a monolithic power splitter, and more particularly, to a monolithic power splitter for splitting a pair of input differential signals into two pairs of output differential signals.
2. Description of the Prior Art
A power splitter is widely applied in the modern electrical system; it is used to split an input signal to two output signals with equal power. Please refer to FIG. 1A. A one-by-two power splitter 2 receives an input signal Si and outputs two output signals So1, So2, wherein the So1 and So2 have equal power. The output signals So1 and So2 are directed to a device 4 via two transmission lines 6 and 8. Similarly, please refer to FIG. 1B. A one-by-two power splitter 10 receives an input signal Si and outputs two output signals So1 and Sot, which are respectively directed to two discrete devices 12 and 14 via two transmission lines 16 and 18. In many applications, the device 4, 12, and 14 may be a receiver, a transformer, or an amplifier, etc. . . .
It is well known that the differential signal, a pair of signals which have equal amplitude and have 180 degree phase difference mutually, can eliminate the transmission noise. Therefore, the differential signal is commonly adopted for the high-quality signal transmission, especially for the Radio Frequency (RF) signal transmission and high-speed signal inter-communication. Therefore, it is popularly utilized in many application fields, such as the telecommunication, Ethernet, the Universal Serial Bus (USB), Display-Port, High-Definition Multimedia Interface (HDMI), etc.
Please refer to FIG. 2. Two separate transmission lines 20 and 22 are used to transmit a pair of differential signals S+ and S− respectively. In general, the length of the transmission lines 20 and 22 is the same to make their transmission impedance be equal, and thus the insertion loss of the differential signal S+ and S− be equal.
Accordingly, a power splitter for a pair of input differential signals needs to be implemented in many situations. Conventionally, it is implemented by utilizing two one-by-two power splitters which are configured in two separate chips. Please refer to FIG. 3. A chipset 30, which is mounted on a printed circuit Board (PCB) 60 and transmits a pair of input differential signals S+ and S− to two one-by-two power splitters 36 and 38 respectively. The two one-by-two splitter 36 and 38 are formed in two discrete chips 40 and 42 respectively, and they split the input differential signal S+ and S− into four output signal S1+, S2+, S1−, and S2− with equal power.
Please continuously refer to FIG. 3. The four output signals S1+, S2+, S1−, and S2− are respectively transmitted to another chipset 52 mounted on the PCB 60 via the transmission lines 44, 46, 48, and 50, which are lied on the PCB 60. In order to achieve the goal of low-noise transmission, the signals S1+, S2+, S1−, and S2− are transmitted in two pairs of differential signals. For example, S1+ and S1− are one pair, and S2+ and S2− is another pair in FIG. 3. Because the two one-by-two power splitters 36 and 38 are formed in two discrete chips 40 and 42, it is very difficult to make the length of the four transmission lines 44, 46, 48, and 50 be equal. Therefore, the four transmission lines 44, 46, 48, and 50 will easily have different transmission impedance. Moreover, the crossed-PCB-routing will make some signal interference with each other. Thus the signals S1+, S2+, S1−, and S2− will have different insertion loss. This is a serious problem needed to be overcome.
Furthermore, such kind of conventional implementation that two one-by-two power splitters are formed in two discrete chips has many other disadvantages including: a. it occupies large PCB space, so it is large and expensive. b. The electrical characteristics of two separated one-by-two power splitters may not be the same since they may be made from different process. c. It needs long transmission length, which will damage the signal quality.
Accordingly, the present invention proposes a monolithic power splitter for splitting a pair of input differential signals into two pairs of output differential signals, which integrates two one-by-two splitters in a single chip made by the single process to overcome the above mentioned problems and disadvantages.